1. Field of the Invention
The present invention relates to a semiconductor device, and, for example, to a semiconductor device that writes data into a memory cell in a negative bit line scheme.
2. Description of the Background Art
As the technology node has been developed, characteristic variations of a MOS (Metal-Oxide-Semiconductor) transistor (hereinafter referred to as a transistor) have also been increasing accordingly. These characteristic variations also occur in the single chip (local variations), which causes a decrease in the operation margin of an SRAM (Static Random Access Memory), thereby making it difficult to achieve lowered operation voltage.
As a method of improving the writing operation margin of the SRAM, there have been several proposals including a scheme of lowering the power supply voltage that is to be supplied to memory cells in a write selection column (a memory cell power supply voltage lowering scheme), and a scheme of applying a negative voltage to a bit line on the low-level side among the bit line pairs in the write selection column (a negative bit line scheme).
In the memory cell power supply voltage lowering scheme, the load capacitance of the memory cell power supply (a diffusion capacitance, a gate capacitance and an interconnection capacitance) is relatively large, which lengthen the time required to lower the power supply voltage in the write selection column to a desired value. This arouses concern about an adverse influence on the cycle time in the case of the memory cell power supply voltage lowering scheme. Furthermore, in the case where the memory cell power supply voltage lowering scheme is applied to a multi-port SRAM, when different line access to the same column occurs (read access by activating a read word line and write access by activating a write word line simultaneously occur in the same column), there occurs a problem that the read margin for the read access line cannot be ensured due to power-down of the memory cell power supply.
As a negative bit line scheme, various configurations are disclosed. Japanese Patent Laying-Open No. 2009-295246 discloses a configuration in which a bit line potential on the low-level side among bit line pairs is detected, and when the bit line potential on the low-level side is lowered to a prescribed value, the negative voltage generated in a negative voltage generation circuit is applied to this bit line on the low-level side. In Japanese Patent Laying-Open No. 2010-218617, and “A Configurable SRAM with Constant-Negative-Level Write Buffer for Low-Voltage Operation with 0.149 μm2 Cell in 32 nm High-k Metal-Gate CMOS” (ISSCC 2010/SESSION 19/HIGH-PERFORMANCE EMBEDDED MEMORY/19.4, pp. 348 to 349) by Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, and Tomoaki Yabe, a bootstrap circuit is disclosed in which, when the potential on the replica bit line having the same capacitance as that on the bit line reaches a prescribed value, the bit line driven to a ground voltage is driven to a negative voltage in a prescribed timing. In “A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment-Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme” (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 3, MARCH 2006, pp. 728 to 742) by Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, and Takakuni Douseki, a negative voltage generation circuit is disclosed in which a negative voltage is overdriven onto a bit line for a prescribed time period.